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Looking at the last 10 years, we see a shift towards multi- and many-core processors. In the 1990s, processor manufacturers were designing monolithic single-core processors and were struggling to increase the performance of this core through extracting more Instruction-Level Parallelism (ILP). However, the cost of extracting more ILP became prohibitively expensive: typically doubling the power consumption for a 20-30% increase in performance. Unfortunately, processor manufacturers realized that they hit this power-wall a bit late. The industry then executed a “right-hand” turn and concentrated on extracting Thread-Level Parallelism (TLP) which is more power-efficient than ILP. To be effective, TLP relies on simpler, lower-power multiple processing cores on a chip executing parallel programs. Therefore, processor manufacturers started putting more cores on chip with each new technology generation doubling the number of cores. To realize the potential of these additional cores requires parallel programming experts; since it is very-difficult to program these multiple processors using current hardware and software. This problem led many to ponder if a programmer-productivity wall is looming in the future. How to design multi-core processors to make them more effective and easier to program is a challenge for computer architects. The research goal of the centre is to let software considerations drive hardware design; we term this top-down Computer Architecture. BSC-Microsoft Research Centre Current Projects One of the initial projects conducted at the centre includes fundamental and applied research in Transactional Memory (TM). The centre developed several TM applications as well as compiler and runtime tools and architectural simulators for TM.

BSC-MSRC Team Looking at the last 10 years, we see a shift towards multi- and many-core processors. In the 1990s, processor manufacturers were designing monolithic single-core processors and were struggling to increase the performance of this core through extracting more Instruction-Level
Parallelism (ILP).

However, the cost of extracting more ILP became prohibitively expensive: typically doubling the power consumption for a 20-30% increase in performance. Unfortunately, processor manufacturers realized that they hit this power-wall a bit late. The industry then executed a “right-hand” turn and concentrated on extracting Thread-Level Parallelism (TLP) which is more power-efficient than ILP. To be effective, TLP relies on simpler, lower-power multiple processing cores on a chip executing parallel programs. Therefore, processor manufacturers started putting more cores on chip with each new technology generation doubling the number of cores.

To realize the potential of these additional cores requires parallel programming experts; since it is very-difficult to program these multiple processors using current hardware and software. This problem led many to ponder if a programmer-productivity wall is looming in the future. How to design multi-core processors to make them more effective and easier to program is a challenge for computer architects.

The research goal of the centre is to let software considerations drive hardware design; we term this top-down Computer Architecture.

BSC-Microsoft Research Centre Current Projects

One of the initial projects conducted at the centre includes fundamental and applied research in Transactional Memory (TM). The centre developed several TM applications as well as compiler and runtime tools and architectural simulators for TM.