Papers by Adria Armejach |
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Circuit Design of a Dual-Versioning L1 Data Cache
Integration, the VLSI Journal
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Dec 2011
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory
In 20th International Conference on Parallel Architectures and Compilation Techniques (PACT'2011)
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Oct 2011
Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency (Best Paper Award)
In 21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11)
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May 2011
EazyHTM, Eager-Lazy Hardware Transactional Memory
42nd International Symposium on Microarchitecture, Micro'09, New York
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Dec 2009
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