Papers by Ibrahim Hur |
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Hardware Transactional Memory with Software-Defined Conflicts
To Appear in 7th International Conference on High-Performance and Embedded Architectures and Compilation (HiPEAC'2012)
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Jan 2012
no files attached
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory
In 20th International Conference on Parallel Architectures and Compilation Techniques (PACT'2011)
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Oct 2011
SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory (poster)
To appear in 20th International Conference on Parallel Architectures and Compilation Techniques (PACT'2011)
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Oct 2011
STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems
In 20th International Conference on Parallel Architectures and Compilation Techniques (PACT'2011)
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Oct 2011
Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency (Best Paper Award)
In 21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11)
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May 2011
TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System
In 19th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011)
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May 2011
From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype
In 7th International Symposium on Applied Reconfigurable Computing (ARC 2011)
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Mar 2011
RMS-TM: A Comprehensive Benchmark Suite for Transactional Memory Systems (Best Paper Award)
The International Conference on Performance Engineering (ICPE 2011)
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Mar 2011
Discovering and Understanding Performance Bottlenecks in Transactional Applications (Best Paper Award)
PACT’10: Proc. 19th International Conference on Parallel Architectures and Compilation Techniques
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Sep 2010
pact2010-zyulkyarov.pdf| pact2010-BestPaperAward.jpeg| tmprofiling-pact2010.pptx| tmprofiling-pact2010.ppt
FaulTM: Fault-Tolerance Using Hardware Transactional Memory
Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture
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Jun 2010
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