Papers by BSC-MSRC |
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TagTM - Accelerating STMs with hardware tags for fast meta-data access
Design, Automation & Test in Europe - DATE 2012
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Mar 2012
The paper will be uploaded when the camera version is ready
no files attached
Hardware Transactional Memory with Software-Defined Conflicts
To Appear in 7th International Conference on High-Performance and Embedded Architectures and Compilation (HiPEAC'2012)
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Jan 2012
no files attached
Circuit Design of a Dual-Versioning L1 Data Cache
Integration, the VLSI Journal
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Dec 2011
Rapid Development of Error-Free Architectural Simulators using Dynamic Runtime Testing
23rd International Symposium on Computer Architecture and High Performance Computing
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Oct 2011
FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware
Workshop on Wild and Sane Ideas in Speculation and Transactions
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Oct 2011
FIMSIM: A Fault Injection Infrastructure for Microarchitectural Simulators
To Appear in the 29th International Conference on Computer Design (ICCD)
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Oct 2011
no files attached
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory
In 20th International Conference on Parallel Architectures and Compilation Techniques (PACT'2011)
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Oct 2011
SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory (poster)
To appear in 20th International Conference on Parallel Architectures and Compilation Techniques (PACT'2011)
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Oct 2011
DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory
To appear in 20th International Conference on Parallel Architectures and Compilation Techniques (PACT 2011)
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Oct 2011
no files attached
STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems
In 20th International Conference on Parallel Architectures and Compilation Techniques (PACT'2011)
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Oct 2011
Interchangeable Back Ends for STM Compilers
6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT)
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Jun 2011
A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory
6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT)
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Jun 2011
Hybrid Transactional Memory with Pessimistic Concurrency Control
International Journal of Parallel Programing, Vol. 39, Issue 3
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Jun 2011
no files attached
Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency (Best Paper Award)
In 21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11)
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May 2011
TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System
In 19th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011)
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May 2011
From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype
In 7th International Symposium on Applied Reconfigurable Computing (ARC 2011)
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Mar 2011
RMS-TM: A Comprehensive Benchmark Suite for Transactional Memory Systems (Best Paper Award)
The International Conference on Performance Engineering (ICPE 2011)
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Mar 2011
Architectural support for Fair Reader-Writer Locking
The 43rd International Symposium on Microarchitecture (MICRO-43)
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Dec 2010
Discovering and Understanding Performance Bottlenecks in Transactional Applications (Best Paper Award)
PACT’10: Proc. 19th International Conference on Parallel Architectures and Compilation Techniques
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Sep 2010
pact2010-BestPaperAward.jpeg| tmprofiling-pact2010.pptx| tmprofiling-pact2010.ppt| pact2010-zyulkyarov.pdf
FaulTM: Fault-Tolerance Using Hardware Transactional Memory
Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture
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Jun 2010
Dynamic Filtering: Multi-Purpose Architecture Support for Language Runtime Systems
Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010)
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Mar 2010
Debugging Programs that use Atomic Blocks and Transactional Memory
15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2010), Bengalore
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Jan 2010
EazyHTM, Eager-Lazy Hardware Transactional Memory
42nd International Symposium on Microarchitecture, Micro'09, New York
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Dec 2009
Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory (Best Paper Award)
11th IEEE International Conference on High Performance Computing and Communications (HPCC-09) June, 2009, Seoul.
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Jun 2009
QuakeTM: Parallelizing a Complex Serial Application Using Transactional Memory
23rd ACM/SIGARCH International Conference on Supercomputing (ICS'09)
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Jun 2009
Clock Gate on Abort: Towards Energy-Efficient Hardware Transactional Memory
Fifth IEEE Workshop on High-Performance, Power-Aware Computing (HP-PAC), 2009
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May 2009
Taking the Heat off Transactions: Dynamic Selection of Pessimistic Concurrency Control
23rd IEEE International Parallel & Distributed Processing Symposium (IPDPS 2009)
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May 2009
Synthesis of a Parallel Smith-Waterman Sequence Alignment Kernel into FPGA Hardware
Many-Core and Reconfigurable Supercomputing Conference, Berlin
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Mar 2009
no files attached
RMS-TM: A Transactional Memory Benchmark for Recognition, Mining and Synthesis Applications
4th ACM SIGPLAN Workshop on Transactional Computing, TRANSACT 2009
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Feb 2009
Atomic Quake: Using Transactional Memory in an Interactive Multiplayer Game Server
14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)
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Feb 2009
Atomic Quake - PPoPP.ppt| Atomic Quake: Using Transactional Memory in an Interactive Multiplayer Game Server
Turbocharging boosted transactions or: How I Learnt to Stop Worrying and Love Longer Transactions
Poster Session, 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)
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Feb 2009
Profiling Transactional Memory applications on an atomic block basis: A Haskell case study
MULTIPROG 2009
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Jan 2009
WormBench - A Configurable Workload for Evaluating Transactional Memory Systems
Workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA), in conjunction with PACT
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Oct 2008
WormBench Presentation| WormBench - A Configurable Workload for Evaluating Transactional Memory Systems
Transactional Memory and OpenMP
International Journal of Parallel Programming
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Sep 2008
no files attached
The Limits of Software Transactional Memory (STM): Dissecting Haskell STM Applications on a Many-Core Environment
ACM International Conference on Computing Frontiers 2008
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May 2008
Nebelung: Execution Environment for Transactional OpenMP
International Journal of Parallel Programming. Vol 36, number 3
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May 2008
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Towards fair, scalable, locking
Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008) in conjunction with GCO
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Apr 2008
Hybrid Transactional Memory to Accelerate Safe Lock-based Transactions
Third ACM SIGPLAN Workshop on Transactional Computing TRANSACT
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Feb 2008
Transactional Memory: An Overview
IEEE Micro
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Jan 2008
no files attached
Multithreaded Software Transactional Memory and OpenMP
Workshop on Memory performance: Dealing with Applications, systems and architecture (Medea) in conjunction with PACT
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Sep 2007
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Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors
Workshop on Operating System support for Heterogeneous Multicore Architectures (OSHMA) in conjunction with PACT
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Sep 2007
Hardware Transactional Memory with Operating System Support, HTMOS
Workshop on Highly Parallel Processing on a Chip in conjunction with Euro-Par
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Aug 2007
Dissecting Transactional Executions in Haskell
Second ACM Workshop on Transactional Computing TRANSACT
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Aug 2007
Abstract Nested Transactions
Second ACM Workshop on Transactional Computing TRANSACT
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Aug 2007
no files attached
Transactional Memory and OpenMP
International Workshop on OpenMP
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Jun 2007
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UnreadTVar: Extending Haskell Software Transactional Memory for Performance
Symposium on Trends in Functional Programming, 2007
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Apr 2007
Compile Time Support for Using Transactional Memory in C/C++ Applications
Workshop on Interaction between Compilers and Computer Architecture
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Feb 2007
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