Publications |
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Papers
TagTM - Accelerating STMs with hardware tags for fast meta-data access
Design, Automation & Test in Europe - DATE 2012
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Mar 2012
The paper will be uploaded when the camera version is ready
no files attached
Hardware Transactional Memory with Software-Defined Conflicts
To Appear in 7th International Conference on High-Performance and Embedded Architectures and Compilation (HiPEAC'2012)
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Jan 2012
no files attached
Circuit Design of a Dual-Versioning L1 Data Cache
Integration, the VLSI Journal
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Dec 2011
Rapid Development of Error-Free Architectural Simulators using Dynamic Runtime Testing
23rd International Symposium on Computer Architecture and High Performance Computing
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Oct 2011
FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware
Workshop on Wild and Sane Ideas in Speculation and Transactions
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Oct 2011
FIMSIM: A Fault Injection Infrastructure for Microarchitectural Simulators
To Appear in the 29th International Conference on Computer Design (ICCD)
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Oct 2011
no files attached
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory
In 20th International Conference on Parallel Architectures and Compilation Techniques (PACT'2011)
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Oct 2011
SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory (poster)
To appear in 20th International Conference on Parallel Architectures and Compilation Techniques (PACT'2011)
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Oct 2011
DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory
To appear in 20th International Conference on Parallel Architectures and Compilation Techniques (PACT 2011)
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Oct 2011
no files attached
STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems
In 20th International Conference on Parallel Architectures and Compilation Techniques (PACT'2011)
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Oct 2011
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