Barcelona Multicore Workshop 2008

Event Date and Time: 
05/06/2008 (All day) - 06/06/2008 (All day)

Barcelona Supercomputing Center (BSC-CNS) and Universitat Politecnica de Catalunya (UPC), Campus Nord, Barcelona

Workshop Program

Speakers and Attendees family picture



Multi-core processors have already arrived and many-cores are just on the horizon. The most important issue facing the software community is how to program those machines in the most productive way. The most important issue facing the hardware community is how to design the many-cores so as to maximize the potential performance. Those issues describe the same challenge facing both communities: how to maximize the effectiveness of many-cores.

The proposed solutions to the above problem require a ultidisciplinary HW-SW participation. The idea of BMW08 was to bring together prominent researchers active across the field – computer architecture, programming languages and formal foundations in the course of a two day multi-core workshop, in Barcelona on June 5-6. The organization of the workshop strived to encourage cross-fertilization of ideas across the HW and SW communities. The BMW08 workshop consisted of a combination of fourteen invited talks, two panel discussions and time for discussion. This is the list of presenters and titles:

  • Ali-Reza Adl-Tabatabai (Intel) Design and Implementation of Transactional Constructs for C/C++
  • Doug Burger (UT-Austin) Decoupled Composable Processors
  • Derek Chiou (UT-Austin) Parallelizing Computer System Simulators
  • Rudi Eigenmann (Purdue) Compiling for Multi, Many and Anycore
  • Simon Green (NVidia) Parallel Computing using NVIDIA CUDA
  • Maurice Herlihy (Brown) Making Transactional Memory More Scalable
  • Peter Hofstee (IBM) Programming Heterogeneous Multicore Processors
  • Jesús Labarta (BSC) StarSs: Portable Programming for a Fuzzy Multicore Space
  • Kunle Olukotun (Stanford) Towards Pervasive Parallelism: Parallel Applications without Parallel Programming
  • Marc Snir (UIUC) UPCRC at Illinois: Making Parallel Programming Synonymous with Programming
  • Per Stenström (Chalmers) Major Hurdles of Hardware Transactional Memory and Some Solutions
  • Marc Tremblay (SUN) Rock architecture and its Hardware Transactional Memory
  • Panagiotis Tsarchopoulos (EC) European Research in Computing

In addition Yale Patt (UT-Austin) and Dan Reed (Microsoft) chaired two exciting panel discussions:

50 Billion Transistor Chips: What should the Hardware provide?
(and what, if anything, should we expect from the Software?), chaired by Yale Patt

For good or for bad, multicore has arrived, and we would like it to provide
benefit. The question is how to make that happen. Part of the answer has
got to be what should the hardware provide. We have already seen multiple
answers, including homogeneous core chips from Sun and Intel (Niagara,
Larrabee), heavy lifting core chips from IBM (Cell), and special
function-added core chips from several companies. Part of the answer also
has to include careful attention to what the interface to the software
should be. Providing a chip that no one can use seems pointless. On the
other hand, expecting nothing from the software seems absurd. After all,
they get paid also. This panel will explore both issues.

What Terrifies You More: Multicore Hardware or Software?, chaired by Dan Reed

We are at a hardware/software technology inflection point, with large-scale chip parallelism upon us.  Will our software approaches be constrained by our fear of radical hardware alternatives that exploit transistors via heterogeneous processing elements?  Will our hardware innovation be constrained by fears of programming difficulties associated with multicore chips?  How do we strike a reasonable balance between hardware exploration and exploitation and programmability, given the existing code base and the rising complexity of new software systems?

The workshop is co-organized by the new BSC-Microsoft Research Center and BSC/UPC as the partners of HiPEAC (European Network on High-Performance and Embedded Architectures and Compilers).

Organizing Committee:

Eduard Ayguade (BSC-UPC)
Tim Harris (Microsoft)
Per Stenstrom (Chalmers)
Philippas Tsigas (Chalmers)

Local Arrangements:

Nacho Navarro (UPC)
Osman Unsal (BSC)