Experiences with High-Level Language Programming of FPGA Accelerators

Walid Najjar (UC-Riverside)

FPGAs have been shown to be very powerful accelerators on a wide range of applications. However, their poor programmability continue to be the main obstacle to their wider adoption. this challenge should be seen in the wider context of the search for a new hardware/software contract in the programming of multicore and heterogeneous platforms. ROCCC (Riverside Optimizing Compiler for Configurable Computing) is an innovative C to VHDL compilation framework specifically focused on FPGA-based code acceleration. Its focus is on compile time transformations and optimizations aimed at generating an efficient circuit from a loop nest. Its objectives are to maximize parallelism within the constraints of the target device, optimize clock cycle time by efficient pipelining and minimize the area utilized. Furthermore, ROCCC relies on extensive and unique loop analysis techniques to increase the reuse of data fetched from off-chip memory. ROCCC 2.0 is a bridges the gap between the temporal programming model inherent in C and the spatial programming model specific to hardware. It is a free and open source tool that supports a modular bottom-up approach and code reuse at multiple levels while maintaining full compatibility with C. It has been demonstrated on a wide variety of applications including signal and image processing, linear algebra and data mining. It has been ported to several platforms including the Convey Computers HC-1 heterogeneous supercomputer.

UC-Walid-FPGA.pdf